Ultimate Productivity for FPGA Logic Design
- Complete front-to-back RTL design environment for Xilinx FPGAs, including the new Virtex®-6 and Spartan®-6 targeted design platforms
- Exclusive features and technologies delivering rapid timing closure for higher performance, and lower power designs
Key Documentation
All Design Tools Documentation
System Requirements
Videos and Webcasts
How to Estimate Power Using XPE and XPA
The ISE® Design Suite: Logic Edition includes exclusive tools and technologies to help achieve optimal design results. These include Intelligent Clock-Gating for dynamic power reduction, Design Preservation for timing predictability, and Partial Reconfiguration for greater system flexibility, size, power, and cost reduction.
ISE Design Suite: Logic Edition Benefits
Achieve Greater Designer Productivity
From product installation through design verification, ISE Design Suite 12 helps you make maximum use of your time and design resources. The ISE Design Suite: Logic Edition provides:
- A complete design environment for your RTL-based design needs with exclusive technologies such as:
- ChipScope Pro and the ChipScope Pro Serial I/O Toolkit for extensive on-chip verification
- ISE™ Simulator, a complete, full-featured HDL simulator integrated within the ISE design environment
- PlanAhead, a complete environment for IO pin planning, floorplanning and detailed graphical design analysis
- Multi-processor support allowing distributed processing to speedup implementation
Attain Breakthrough Performance, Power and Cost Benefits
ISE Design Suite: Logic Edition 12 delivers easy to use technologies to help you achieve even the most aggressive performance goals in less time:
- SmartGuide reduces incremental runtimes by up to 2X by leveraging previous successful implementations
- SmartXplorer leverages distributed processing in a Linux network to identify optimal implementation settings for a design and achieve up to a 38% improvement in design performance
- PlanAhead Design and Analysis Tool, providing complete design control for timing closure, allowing multiple views of a design’s timing critical regions and ultimately providing the means to divide a larger design into smaller blocks and focus efforts towards optimization of each module.
- Design Preservation is a flow for complex designs that preserves implementation results of a module for use in the next implementation iteration
- Enabling lower system cost with an intuitive partial reconfiguration design flow to fit designs into smaller devices and reduce total cost and power
ISE Design Suite provides the tools and technologies to help you manage power for your FPGA design with early accurate power estimation and with power optimization:
- Advanced synthesis and implementation algorithms deliver lower dynamic power
- With goal-based implementation, the ISE Design Suite offers a simple, one-step process to specify power optimization
- Free, downloadable Xpower Estimator spreadsheets for the leading Xilinx FPGAs lets customers quickly and easily estimate their project's power consumption with device-specific spreadsheet tools.
- Xpower Analyzer included with all configuration of ISE performs detailed design-based power consumption analysis, including importing simulation files for detailed design accuracy
- Find answers to your power-related questions at Xilinx Power Solutions, www.xilinx.com/power
Focus on Design Differentiation
The ISE Design Suite: Logic Edition is a comprehensive suite supporting the Base methodology for optimal logic and connectivity design. The ISE Design Suite: Logic Edition delivers an integrated development environment of software tools, configuration wizards, and IP that facilitates your design and utilizes all of the flexibility offered by a programmable platform. The ISE Design Suite helps remove design hurdles enabling you to more easily achieve your design goals.
Xilinx CORE Generator™ System, included in all Editions of the ISE Design Suite, accelerates design time by providing access to highly parameterized Intellectual Properties (IP) and Architecture Wizards with built-in intelligent for functions like I/O and Clocking for Xilinx FPGAs. The available user-customizable IP functions range in complexity from commonly used functions, such as memories and FIFOs, to system-level building blocks, such as filters and transforms. Using these IP blocks can save days to months of design time. The highly optimized IP allows FPGA designers to focus efforts on building designs quicker while helping bring products to market faster.
ISE Design Suite Features
Highlighted rows indicates features included in the ISE Design Suite: Logic Edition.
* Fourth generation Partial Reconfiguration can be purchased as an option and is bundled with two days of onsite training
